![]() Google Patents US7554347B2 - High input/output density optoelectronic probe card for wafer-level test of electrical and optical interconnect components, methods of fabrication, and methods of use 1) and a variety of bump materials-including new lead-free compounds needed to meet the leadfree mandates of the European community.US7554347B2 - High input/output density optoelectronic probe card for wafer-level test of electrical and optical interconnect components, methods of fabrication, and methods of use Today, the wafer test engineer faces bump pitches as low as 150um (Fig. C,4 processes, and no longer consists of only 250um-pitch, high-temperature-melting (290C), high-lead-content solder bumps. Flip-chip packages are also appearing in consumer applications that need to minimize the physical footprint.įlip-chip packaging technology itself is evolving rapidly, progressing beyond the traditional IBM Corp. As other computing and networking applications increase in performance, flip-chip-style pad layouts will spread to graphics, network, and game processors. With a flip-chip interconnect, the interconnect bumps are placed throughout the die, not just on the periphery as with wire-bond pack aging, so the die can be shrunk smaller, despite increased I/O.įlip-chip packaging is now common in high-performance, highpower applications such as microprocessors. IC designers, however, are increasingly choosing flip-chip technology to provide expanded off-chip interconnect. Wire-bond packaging remains the preferred packaging interconnect technology today due to its flexibility, lower cost, and the widespread infrastructure built to support it. The combination of smaller die sizes and increased I/O requirements with the sub-130nm generation will push IC designers to fit more off-chip interconnect pads into a smaller area. Despite the increase in functionality and increase in I/O needs, SoC die sizes are shrinking as process advances reduce die size faster than rising transistor counts can increase them. While the complexity of SoCs grows, designers are forced to steadily increase I/O interconnect pins, driving up the total pin count of each device. Even low-end chips now come with sophisticated embedded processors, glue logic, basic analog, and embedded flash and DRAM memory. New test methodologies are being developed to leverage contact technologies that enable higher parallelism and lower the cost of test (COT) while meeting the rapidly evolving technical challenges posed by trends in IC manufacturing.Īs system on a chip (SoC) devices become prevalent in the industry, more system functionality is being supported on a single piece of silicon. To illustrate the point, a small number of server microprocessors in production in 2003 require that >6000 pins be tested during probe, creating significant challenges for current wafer probe card technologies. High-performance computing and network devices such as microprocessors, graphics processors, network processors, and ASICs are leading the trend, requiring higher wafer test pin counts as power, ground, and input/output (I/O) pin numbers escalate. This article surveys the trends impacting wafer test today and the industry's response to these challenges.Īs Moore's Law continues to shrink device features, the rapidly increasing volume of transistors/chip creates a constant rise in the pin count/drip. ![]() Meanwhile, technical requirements for contact technologies are escalating and the rapid growth of 300mm wafer manufacturing is flooding wafer test areas with additional die, driving the need for innovative techniques to increase capacity and control capital equipment cost. OVERVIEW New semiconductor materials, alternative pad constructions, and ever-shrinking geometries are driving up the complexity and the cost of wafer test.
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